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A Closer Look at Ice Lake Architecture Overview

Learn all about our forthcoming 3rd Generation Intel® Xeon® Scalable Processor (2S) – as Irma Esmer Papazian, Senior Principal Engineer at Intel Corporation, leads a technical discussion on the architecture of this new generation of processor. Explaining how the processer delivers scalable and balanced throughput and per-core performance across a range of HPC workloads. Topics include the new core microarchitecture, crypto acceleration instructions memory and PCIe controllers, security and Intel® AVX frequency improvements and a new profile for Intel® Speed Select Technology. Irma Esmer Papazian, Senior Principal Engineer at Intel Corporation

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